Download CMOS Telecom Data Converters by Roberto Rivoir (auth.), Angel Rodríguez-Vázquez, Fernando PDF

By Roberto Rivoir (auth.), Angel Rodríguez-Vázquez, Fernando Medeiro, Edmond Janssens (eds.)

CMOS Telecom information Converters compiles the most recent achievements concerning the layout of high-speed and high-resolution information converters in deep submicron CMOS applied sciences. The 4 sorts of analog-to-digital converter architectures mostly present in this enviornment are lined, specifically sigma-delta, pipeline, folding/interpolating and flash. For most of these varieties, most recent achievements in regards to the answer of serious architectural and circuital concerns are offered, and illustrated via IC prototypes with measured state of the art performances. a few of these prototypes are conceived to be hired on the chipset of most recent new release wireline modems (ADSL and ADSL+). Others are meant for instant transceivers. in addition to analog-to-digital converters, the ebook additionally covers different capabilities wanted for communique platforms, comparable to digital-to-analog converters, analog filters, programmable achieve amplifiers, electronic filters, and line drivers.

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CMOS Telecom Data Converters

CMOS Telecom information Converters compiles the newest achievements in regards to the layout of high-speed and high-resolution facts converters in deep submicron CMOS applied sciences. The 4 sorts of analog-to-digital converter architectures generally present in this enviornment are lined, particularly sigma-delta, pipeline, folding/interpolating and flash.

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In a few words, conversion speed is lost because not all blocks are "busy" all the time. Pipelining is another technique tending to increase the speed of the converter, by keeping all the blocks busy, all the time [13]. In Fig. 24, the coarse and the fine quantizer are pipelined by the insertion of the two SlHs, SH3 and SH4. The input signal, after being sampled at 26MHz by the first two interleaved S/H, SHI and SH2, is "re-transmitted", still at a rate of 26MHz, to the fine flash ADC with a delay of a clock cycle, owing to a re-sampling carried out by SH3, SH4.

As said before, the converter type determines the architecture of the overall conversion channel. In the case of sigma-delta AID converters, a simple and low-order filtering before conversion, featuring just the anti-aliasing requirement, will be performed, while the required voice-band filtering, after decreasing the sample rate with multi-rate decimation filters, will take place in the digital domain (similar considerations NYQUIST RATE CONVERTERS: AN OVERVIEW 3 apply for the DAC channel). In the case of successive approximation ADC, a full voice-band filtering can be performed in the analog domain, for example through switched-capacitor analog filters.

20) It is worth noting that: I) d output word is not dependent on felk accuracy, since the architecture is based on a ratio of counts, more than an absolute number of counts. This is peculiar of the dual ramp integrating ADC, instead of the single ramp integrating ADC, which performs just an absolute number of counts and does show sensitivity to master clock accuracy. 2) The converter accuracy depends directly on the Vref accuracy, its stability during the conversion as well as long term stability.

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